東京大学 情報理工学系研究科 電子情報学専攻 2023年8月実施 専門 第2問

标签：

• Tokyo-University
• Mealy-Sequence-Detector-State-Minimization
• Karnaugh-Map-Minimization

Author

Josuke

Description

Consider designing a binary digital synchronous sequential circuit as follows.

• The circuit has $2$ inputs $(X_1,X_0)$ and $1$ output $(Z)$.
• The inputs $(X_1,X_0)$ represent a character from $A$ to $D$ encoded as $A = (0,0), B = (0,1) , C = (1,0)$ , and $D = (1,1)$.
• The output $Z$ is $1$ when the last two consecutive inputs are $AA , AC , CB , CD , DA ,$ or $DC$; otherwise $Z$ is $0$.

Answer the following questions.

(1) Explain in $50$ words or less what a synchronous sequential circuit is.

(2) Draw a state transition diagram of the circuit in the form of a Mealy graph. Use $4$ states corresponding to each character. Each state represents that the corresponding character is the last input.

(3) The output $Z$ must be $0$ until the first two characters are given as inputs to the circuit. Answer which state in the state transition diagram in (2) should be the initial state to achieve this.

(4) Simplify the state transition diagram in (2) so that it has $3$ states.

(5) Create a state transition table from the state transition diagram in (4).

(6) Draw Karnaugh maps from the state transition table in (5).

(7) Simplify the logic as much as possible using the Karnaugh maps in (6), and draw the circuit using MIL simbols shown in the Fig.

Kai

(1)

Synchronous sequential circuits are digital circuits that use clock signals to determine the timing of their operations.

(2)

(3)

State $B$ should be the initial state. Since any two consecutive input $BX$ only inputs $0$.

(4)

(5)

(6)

(7)