Let us design a circuit that adds a 4-bit signed integer and a 3-bit signed integer and outputs a 4-bit signed integer .
Two's complement is used to represent signed integers. Let , and be the MSB(Most Significant Bit). Answer the following questions.
(1) Show the ranges of possible values of and in decimal notation.
(2) Show the truth table for the 1-bit full adder shown on the left side of the figure below.
Let and be operands, be the input carry, be the output, and be the output carry.
(3) Show the circuit that computes by combining the full-adder symbols used in (2).
Also, show the input/output signal lines. You can use supply voltage V and ground GND if necessary.
(4) Let us add an overflow detection function to the circuit in (3).
The additional circuit takes a 1-bit signal as output, with when an overflow occurs and otherwise.
Show the truth table of the circuit to output by using necessary signals.
Also, show the circuit that generates by combining necessary signals and gates from , AND, OR, and NOT shown on the right side of the figure below.
The number of gates and inputs can be increased, but the circuit should be simple.
(5) Let us design a circuit to compute instead of adding and .
Show the circuit by combining full-adders, AND, OR, and NOT gates.
Similar to (3), input/output signal lines should also be shown.
You can use V and GND if necessary.
(6) Let us add an overflow detection function to the circuit in (5) as in (4).
The additional circuit takes a 1-bit signal as output, with when an overflow occurs and otherwise.
Show the truth table of the circuit to output by using necessary signals.
Also, show the circuit that genrates by combining necessary signals and gates from , AND, OR, and NOT shown on the right side of the figure below. The number of gates and inputs can be increased, but the circuit should be simple.
