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京都大学 情報学研究科 通信情報システム専攻 2022年8月実施 専門基礎A [A-7]

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Author​

SUN

Description​

Answer all the following questions.

(1)​

Answer the following questions on binary number representations.

(a) Express the following decimal numbers in 8-bit two’s complement representation.

  • (i) +45
  • (ii) -90

(b) Convert the following 8-bit two’s complement binary numbers into 8-bit sign-and-magnitude binary representation.

  • (i) 11110000
  • (ii) 00001111

(c) Show the results of the following addition and subtraction in the 8-bit sign-and-magnitude binary number system.

  • (i) 11110000 + 11110000
  • (ii) 11110000 - 00001111

(d) Show the results of the following addition and subtraction in the 8-bit two’s complement binary number system.

  • (i) 11110000 + 11110000
  • (ii) 11110000 - 00001111

(2)​

Answer the following questions on floating-point numbers represented in IEEE754 half-precision basic format (with 1-bit sign, 5-bit exponent (bias=15) and 10-bit significand).

(a) Show the values of the following floating-point numbers represented in IEEE754 half-precision basic format by the binary scientific notation (e.g., +1.0101010101×2−3+1.0101010101 \times 2^{-3}).

  • (i) 0100 0001 0101 0101
  • (ii) 1000 0001 0101 0101

(b) Represent -9.625 in IEEE754 half-precision basic format.

(3)​

Explain ‘addressing modes’ in an instruction set architecture of a computer.

(4)​

Consider a processor with load/store architecture which has a 5-stage instruction pipeline and operates with a 2 GHz clock. Assume that the processor is stalled for one clock cycle when the result of a load instruction is used by the next instruction, when a ‘branch’ is taken, or when a ‘jump’ is done, and there is no other pipeline hazard. Calculate the execution time of a program by assuming that the number of executed instructions is 1,000,000, the instruction-mix is ALU: 50%, load: 20%, store: 15%, branch: 10%, and jump: 5%, and the ratio of load-use stalls is 40% and the ratio of branches taken is 50%. (Calculate also the derivation process of your answer.)

题目描述​

回答全部问题。

  1. 二进制数表示：
    1. 将十进制 +45+45、−90-90 写成 8 位补码。
    2. 将 8 位补码 11110000、00001111 转换为 8 位原码。
    3. 在 8 位原码体系中计算： (i) 11110000 + 11110000； (ii) 11110000 − 00001111。
    4. 在 8 位补码体系中计算同样两式。
  2. IEEE 754 半精度基本格式含 1 位符号、5 位指数（偏置为 15）和 10 位尾数。
    1. 将下列位串的值写成二进制科学计数法（例如 +1.0101010101×2−3+1.0101010101\times2^{-3}）： (i) 0100 0001 0101 0101； (ii) 1000 0001 0101 0101。
    2. 用 IEEE 754 半精度表示 −9.625-9.625。
  3. 说明计算机指令集架构中的寻址方式。
  4. 某 load/store 处理器采用五级流水线，时钟频率为 2 GHz2\,\mathrm{GHz}。若 load 结果被下一条指令使用、分支被采用或执行 jump，均停顿 1 周期，且无其他冒险。程序执行 1,000,0001{,}000{,}000 条指令，指令比例为 ALU 50%50\%、load 20%20\%、store 15%15\%、branch 10%10\%、jump 5%5\%；load-use 停顿比例为 40%40\%，分支采用比例为 50%50\%。求执行时间，并写出推导过程。

考点​

  • 补码、原码与定长运算：完成有符号表示转换和加减法，判断表示范围与溢出。
  • IEEE 754 半精度浮点数：解析符号位、偏置指数和隐含首位，并把十进制小数编码为半精度位串。
  • 寻址方式：说明不同指令如何由寄存器、立即数及地址计算取得操作数。
  • 流水线性能：按指令混合与各类停顿比例计算额外周期，再用时钟频率换算执行时间。

Kai​

(1)​

(a)​

  • (i) (+45) = (00101101)
  • (ii) (-80) = (10100110)

(b)​

  • (i) (10010000)
  • (ii) (00001111)

(c)​

  • (i) Overflow
  • (ii) (11111111)

(d)​

  • (i) (11100000)
  • (ii) (11100001)

(2)​

(a)​

(i) Sign bit: 0 Exponent: 10000 (Real value = 16 - 15 = 1) Mantissa: 01010101 => +1.01010101×21+1.01010101 \times 2^1

(ii) Sign bit: 1 Exponent: All zero -> This is not a normalized number. Mantissa: Not zero => −0.01010101×2−14-0.01010101 \times 2^{-14}

(b)​

Sign bit: 1, -8.625 in scientific notation: −1.00011×23-1.00011 \times 2^3 Exponent: 10010, Mantissa: 00110000 => 1100 1000 1110 0000

(3)​

① Immediate Addressing: The operand is specified directly within the instruction itself.

② Register Addressing: The operand is held in a specific CPU register, and the instruction identifies that register.

③ Direct Addressing: The instruction contains the absolute memory address where the operand is stored.

④ Indirect Addressing: The instruction specifies a register or memory location that contains the effective address of the operand.

⑤ Displacement Addressing: The effective address is calculated by adding an offset (displacement) to the contents of a base register.

(4)​

Clock cycle ≈5×10−10\approx 5 \times 10^{-10} s Load-use stalls: 1×106×0.2×0.4=0.08×1061 \times 10^6 \times 0.2 \times 0.4 = 0.08 \times 10^6 clock cycles Control hazard stalls: 1×106×(0.2×0.5+0.05)=0.15×1061 \times 10^6 \times (0.2 \times 0.5 + 0.05) = 0.15 \times 10^6 clock cycles

Total Time = 1.23×106×5×10−101.23 \times 10^6 \times 5 \times 10^{-10} s = 6.15×10−46.15 \times 10^{-4} s

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